The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. One such step is referred to as a post exposure bake step, which follows a masking step.
The masking step is used to protect one area of the wafer while working on another area. This process is referred to as photolithography or photo-masking. A photo resist, or light-sensitive film, is applied to the wafer, giving it characteristics similar to a piece of photographic paper. Depending on the resist system, post exposure baking may be employed to reduce standing wave effects and/or to thermally catalyze chemical reactions that amplify a latent image. Post exposure baking has been shown to increase linewidth control and resolution. Conventionally, post exposure baking times and/or temperatures have been pre-calculated and/or based on indirect measurements (e.g., concentration of chemicals in vapor retrieved from post exposure bake chamber). Such pre-calculated control parameters and/or indirect measurements may not, therefore, account for wafer-to-wafer variations, variations within a wafer and/or apparatus idiosyncrasies, for example.
In an etching step, the wafer is then “developed” (the exposed photo resist is removed) and baked to harden the remaining photo resist pattern. The temperature at which the wafer is baked, and the period of time for which it is baked affect the critical dimensions of the wafer. The wafer is then exposed to a chemical solution or plasma (gas discharge) so that areas not covered by the hardened photo resist are etched away. The photo resist is removed using additional chemicals or plasma and the wafer is then inspected to ensure the image transfer from the mask to the top layer is correct.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the post exposure bake temperature and the time period over which one or more temperatures are applied during the post exposure bake are significant factors in achieving desired critical dimensions. It has been demonstrated that the post-exposure bake step is important in IC manufacture since it can be employed to activate chemical reactions that catalyze the amplification of an initial UV-light induced latent image. Within-wafer and/or wafer-to-wafer variations during post-exposure bake will contribute significantly to linewidth variation. Thus, maintaining the post exposure bake at a desired temperature, for a desired period of time, may enable uniformity in photo resist hardening and increase the quality of the underlying integrated circuit being manufactured. Small changes in the time and temperature history of the post exposure bake can substantially alter photo resist hardening, resulting in lack of image line control. For example, a few degrees temperature difference and/or an overly long or short post exposure bake time can drastically affect critical dimensions.
To keep processing times under control, sensitive photo resists are employed. A typical highly sensitive photo resist is a chemically amplified photo resist. A chemically amplified photo resist is one in which exposure to actinic radiation produces a catalyst for a reaction that alters the solubility of the resist. A common example is a positive tone resist containing a photo acid generator that generates an acid catalyst on exposure to actinic radiation. The photo-generated acid may catalyze a deprotection reaction that increases the solubility of the photo resist in an aqueous base.
A post exposure baking (PEB) step can be employed to cause the photo-generated catalyst to diffuse and react within the photo resist coating. The PEB step has a significant effect on the quality of pattern transfer. If the PEB step is too long, or if the resist is overheated, then the catalyst can migrate outside of the exposed portion of the resist into surrounding unexposed areas. If the PEB step is too short or the resist is under heated, diffusion and reaction of the catalyst may be unduly limited resulting in an inadequate solubility contrast between exposed and unexposed regions of the photo resist.
Time and temperature are related in the post exposure bake process. For example, higher temperatures may cause faster baking and subsequently faster hardening, while lower temperatures may cause slower baking and correspondingly slower hardening. Ideally, all portions of a wafer would bake and harden at precisely the same rate when subjected to identical temperatures for identical times. Unfortunately, such uniform baking and hardening does not always occur, with different wafer portions baking and hardening at different rates. For example, the center of a wafer may bake and harden at a different rate than the edge of a wafer. Thus, an efficient system and/or method to monitor the post exposure bake and hardening process, and to control post exposure baking time and temperature, is desired to increase fidelity in image transfer.